Summary

Introduction

When in the course of human events it becomes necessary to mix analog and digital circuit on the same chip, some care must be taken to prevent the digital from destroying the analog. The main culprit in this saga is the following circuit, the CMOS inverter and it’s brethern, the CMOS logic gates.

Figure 1 - The Evil Doer

It is the action of this circuit and it’s effect on the power supply when it switches from one state to the other, that concerns us. When switching occurs, a large current flows either from the power supply to the output, or from the output to the ground, depending on which logic transition is occurring. The current goes from zero to a large value and then back to zero, in a short period of time.  I will illustrate the problem using a simulation.

Simulation

Discussion

Given a perfect power supply net – i.e. one with no resistance and zero inductance, this would not be a problem.We don’t have that and so it is a problem. The large, rapid current change causes a momentarily large voltage across the supply impedance, reducing the effective supply voltage for the switching cell and every other one in it’s proximity. As such, the performance of adjacent cells is affected whenever one of them switches. The extent of this disturbance depends on the power and ground impedance, that is on the layout of the supply nets, and the number of logic cells that are switching simultaneously. In a large SOC the number of logic gates that transition at the same time could be thousands, or millions.